1. Field of the Invention
The present invention relates to a DAC circuit (Digital-to-Analog converting circuit).
2. Description of Related Art
FIG. 12 is a circuit diagram of a ring oscillator using a conventional DAC circuit, and in the figure, reference numeral 1 signifies the DAC circuit that outputs analog currents Idac 1 and Idac 2 according to digital codes into two split routes.
Reference numerals 2a to 2d signify a differential amplifier connected in a ring, and 3 signifies a composite circuit composed of two differential amplifiers, which outputs a signal voltage obtained by adjusting the ratio of a signal voltage from the differential amplifier 2b to a signal voltage from the differential amplifier 2d in accordance with the analog currents Idac 1 and Idac 2 and thereafter adding the outputs of the above two differential amplifiers. The differential amplifiers 2a, 2b, and one of the differential amplifiers inside the composite circuit 3 constitute a three-stage ring oscillator; and the differential amplifiers 2a to 2d and the another differential amplifier inside the composite circuit 3 constitute a five-stage ring oscillator.
In addition, in the DAC circuit 1, reference numeral 11 denotes a p-channel FET having a source connected to a power supply VCC and having a drain connected to a constant current source 12, 13 to 16 each denote the p-channel FET having each source connected to the power supply VCC and having each gate connected commonly to a gate of the p-channel FET 11, and each p-channel FET constitutes a current mirror circuit together with the p-channel FET 11. These p-channel FETs 13 to 16 are provided in correspondence with each bit of input digital codes. For example, when the input digital codes are 4 bits in total, namely, from bit 0 to bit 3, the DAC circuit 1 includes four p-channel FETs 13 to 16, as shown in FIG. 12. Further, with regard to the p-channel FETs 13 to 16, the transistor number (transistor size) is produced in correspondence with the corresponding bit thereof. For example, if the transistor number of the p-channel FET 16 corresponding to bit 0 is assumed to be Scale=1, the transistor number of the p-channel FET 15 corresponding to bit 1 is produced in Scale=2, the transistor number of the p-channel FET 14 corresponding to bit 2 is produced in Scale=4, and the transistor number of the p-channel FET 13 corresponding to bit 3 is produced in Scale=8, and further the transistor number of the p-channel FET 11 of the current mirror circuit source is produced in Scale=50.
Reference numerals 17 to 20 each denote a switch that switches the analog current from the corresponding drain of the p-channel FETs 13 to 16 in correspondence with the input digital code between two routes of analog currents Idac 1 and Idac 2, which are supplied to the composite circuit 3.
FIG. 13 is a table chart of the relation between the digital codes and the analog currents Idac 1, Idac 2 of the conventional DAC circuit.
FIG. 14 includes a characteristic chart of the relation between the digital codes and the analog currents Idac 1, Idac 2 of the conventional DAC circuit, and a characteristic chart of the relation between the digital codes and the oscillation frequency of the ring oscillator using the DAC circuit of the same.
FIG. 15 includes a characteristic chart of the relation between the digital codes and the analog currents Idac 1, Idac 2 of an ideal DAC circuit, and a characteristic chart of the relation between the digital codes and the oscillation frequency of the ring oscillator using the DAC circuit of the same.
Next, the operation will be explained.
In the DAC circuit 1, the p-channel FET 11 of the current mirror circuit source connected to the constant current source 12 has the transistor number produced in Scale=50, 50 xcexcA constantly flowing through the p-channel FET 11.
In the p-channel FETs 13 to 16 connected in the current mirror connection configuration with the p-channel FET 11, a constant current according to each transistor number flows through the corresponding transistor. That is, the transistor number of the p-channel FET 13 is Scale=8, 8 xcexcA constantly flowing through the p-channel FET 13; the transistor number of the p-channel FET 14 is Scale=4, 4 xcexcA constantly flowing through the p-channel FET 14; the transistor number of the p-channel FET 15 is Scale=2, 2 xcexcA constantly flowing through the p-channel FET 15; and the transistor number of the p-channel FET 16 is Scale=1, 1 xcexcA constantly flowing through the p-channel FET 16.
The switches 17 to 20 switch the analog currents from the drains of the p-channel FETs 13 to 16, respectively, in correspondence with the input digital codes. For example, if the digital code is xe2x80x9c0xe2x80x9d, the side of the analog current Idac 2 will be selected; if the digital code is xe2x80x9c1xe2x80x9d, the side of the analog current Idac 1 will be selected.
FIG. 13 illustrates the relation between the digital codes and the analog currents Idac 1, Idac 2 in that case. Thus, the analog currents Idac 1, Idac 2 produced by the DAC circuit 1 varies uniformly in accordance with the digital codes, and variations in the analog currents Idac 1, Idac 2 for the 1 LSB of the digital codes is constant relative to all the values of the digital codes.
In the ring oscillator, the differential amplifiers 2a, 2b, and one of the differential amplifiers inside the composite circuit 3 constitute the three-stage ring oscillator that generates higher frequencies; and the differential amplifiers 2a to 2d and the other inside the composite circuit 3 constitute the five-stage ring oscillator that generates lower frequencies.
The composite circuit 3 adjusts the ratio of a signal voltage from the differential amplifier 2b to a signal voltage from the differential amplifier 2d in accordance with the analog currents Idac 1 and Idac 2 supplied from the DAC circuit 1, thereafter adds the outputs of the above two differential amplifiers, and outputs the result as a signal voltage. For instance, if the analog current Idac 1 is 0 xcexcA and the analog current Idac 2 is 15 xcexcA, the composite circuit 3 will output a signal voltage acquired by decreasing the weighting of the signal voltage from the differential amplifier 2b and increasing the weighting of the signal voltage from the differential amplifier 2d and then adding both the results; and if the analog current Idac 1 is 15 xcexcA and the analog current Idac 2 is 0 xcexcA, the composite circuit 3 will output a signal voltage acquired by increasing the weighting of the signal voltage from the differential amplifier 2b and decreasing the weighting of the signal voltage from the differential amplifier 2d and then adding both the results.
The left characteristic chart in FIG. 14 illustrates the relation between the digital codes and the analog currents Idac 1, Idac 2 of the DAC circuit 1 illustrated in FIG. 12, which is a graphic expression of the table illustrated in FIG. 13. The right characteristic chart in FIG. 14 illustrates the relation between the digital codes input to the DAC circuit 1 and the oscillation frequency output from the composite circuit 3, when the ring oscillator is controlled using the analog currents Idac 1, Idac 2 according to the digital codes.
Since the conventional DAC circuit is configured as above, the analog currents Idac 1, Idac 2 produced by the DAC circuit 1 varies uniformly in accordance with the digital codes, and the variations in the analog currents Idac 1, Idac 2 for the 1 LSB of the digital codes is constant relative to all the values of the digital codes.
However, when the oscillation frequency of the ring oscillator is controlled using the analog currents Idac 1, Idac 2, the oscillation frequency of the ring oscillator does not vary constantly relative to the variations in the analog currents Idac 1, Idac 2; and as illustrated in the right characteristic chart in FIG. 14, the variations in the oscillation frequency are decreased on the side of the smaller digital codes, and the variations in the oscillation frequency are increased on the side of the greater digital codes. In consequence, the controllability is not stabilized.
Therefore, there has been a requirement for a DAC circuit having the characteristics such that the relations between the digital codes and the analog currents Idac 1, Idac 2 are swollen upward in a convex form, as illustrated in the left characteristic chart in FIG. 15, and the relation between the digital codes and the oscillation frequency varies constantly, as illustrated in the right characteristic chart in FIG. 15.
In view of the foregoing, the present invention has been made, and an object of the invention is to provide a DAC circuit that outputs more analog currents around a medium value of the digital codes as compared with a conventional DAC circuit.
According to one aspect of the invention, a digital-to-analog converting circuit including: a first transistor group composed of a plurality of transistors, which causes a constant current to flow through the plurality of transistors; a second transistor group composed of a plurality of transistors corresponding to each bit of digital codes, and composing a current mirror circuit together with the first transistor group; and a control circuit that perform a control by which a number of transistors to be turned ON in the first transistor group is decreased around a medium value of the digital codes input, and the number of transistors to be turned ON in the first transistor group is increased around the minimum value and the maximum value of the digital codes, and the second transistor group outputs analog currents according to the digital codes into two split routes.
According to another aspect of the invention, a digital-to-analog converting circuit including: a first transistor group composed of a plurality of transistors, which causes a constant current to flow through the plurality of transistors; a second transistor group composed of a plurality of transistors, which causes a constant current to flow through the plurality of transistors; a third transistor group composed of a plurality of transistors corresponding to each bit of digital codes, and composing a current mirror circuit together with the first transistor group, in which the transistors corresponding to each bit of the input digital codes operate in accordance with the input digital codes so as to output an analog current in accordance with the digital codes; a fourth transistor group composed of a plurality of transistors corresponding to each bit of digital codes, and composing a current mirror circuit together with the second transistor group, in which the transistors corresponding to each bit of the input digital codes operate in accordance with the input digital codes in a manner reverse to the third transistor group to output an analog current in accordance with the digital codes; and a control circuit that performs control by which the number of transistors to be turned ON in the first transistor group is increased and to increase the number of transistors to be turned OFF in the second transistor group is increased, while the input digital codes are increased from the minimum value to the maximum value.
By these arrangement these DAC circuit outputs more analog currents than a conventional DAC circuit around the medium value of the digital codes, and if the analog current outputs that are split into two routes are supplied to a ring oscillator from this DAC circuit, it is possible to make the variations in the finally obtained oscillation frequency relative to the digital codes linear.
According to further aspect of the present invention a digital-to-analog converting circuit is characterized by that the first transistor group is composed of a plurality of transistors corresponding to only a plurality of upper bits except for the most significant bit of the digital codes, and the control circuit controls the operation of the plurality of transistors in the first transistor group on the basis of the most significant bit of the input digital codes and the plurality of upper bits.
According to more further aspect of the present invention a digital-to-analog converting circuit is characterized by that first transistor group and the second transistor group are respectively composed of a plurality of transistors corresponding to only a plurality of upper bits of the digital codes, and the control circuit controls the operation of the plurality of transistors in the first and second transistor groups on the basis of the plurality of upper bits of the input digital codes.
By these arrangement deleting the transistors corresponding to the lower bits of the first and/or second transistor groups will lead to an effect of reducing a layout size as well as a chip size.